Implementing electronic circuits involves connecting isolated devices through specific electronic paths. In silicon integrated circuit fabrication it is necessary to isolate devices, which are built into the same silicon matrix, from one another. They are subsequently interconnected to create the desired circuit configuration. In the trend toward integrated circuits of continually higher density, parasitic inter-device currents become more problematic. Thus, isolation technology has become one of the most critical aspects of contemporary integrated circuit fabrication.
Over the last few decades a variety of successful isolation technologies have been developed to address the requirements of different integrated circuit types, such as NMOS, CMOS and bipolar. In general, the various isolation technologies exhibit different attributes with respect to such characteristics as minimum isolation spacing, surface planarity, process complexity and defect density generated during the isolation processing. Moreover, it is common to trade off some of these characteristics when developing an isolation process for a particular integrated circuit application.
In metal-oxide-semiconductor (MOS) technology it is necessary to provide an isolation structure that prevents parasitic channel formation and leakage currents between adjacent devices, such devices being primarily NMOS or PMOS transistors or CMOS circuits. The most widely used isolation technology for MOS circuits has been that of LOCOS isolation, an acronym for LOCal Oxidation of Silicon. LOCOS isolation essentially involves the growth of recessed or semirecessed silicon dioxide (SiO.sub.2 or oxide) in unmasked nonactive or field regions of the silicon substrate producing the so-called field oxide (FOX). The masked regions of the substrate generally define active areas (AA) within which devices are subsequently fabricated. The FOX is generally grown thick enough to minimize parasitic capacitance and prevent parasitic devices from forming in these regions, but not so thick as to cause step coverage problems. The great success of LOCOS isolation technology is to a large extent attributed to its cost effectiveness and the inherent simplicity of incorporating the process into conventional MOS process integration.
An exemplary prior art LOCOS isolation process is illustrated in FIGS. 1-2. As shown in FIG. 1, a silicon substrate 20 is typically masked by a so-called masking stack 22 comprising a pad-oxide layer 23 and a masking nitride layer 24 (Si.sub.3 N.sub.4). The masking stack 22 is typically patterned by conventional photolithographic means and etched to expose selected regions of the silicon substrate 20 for FOX growth. As shown in FIG. 2, an exemplary active area array 30 is defined and protected from oxide growth by the patterned masking stack segments 32. Field isolation of the active areas is achieved by growing FOX in the unmasked portions (e.g., 31 and 34) of the silicon substrate. Typical parameters for the oxidation step include heating at about 1,000.degree. C. for about 2-4 hours in the presence of oxygen, as disclosed in Wolf, "Silicon Processing for the VLSI Era; Volume 2--Process Integration," Lattice Press, for example. After FOX growth, the masking stack segments 32 are removed and devices are fabricated within the active areas.
In one variation, termed recessed LOCOS, a trench may be etched within the silicon substrate, and the walls of the trench are oxidized to provide the electrically isolating field oxide around the perimeter surfaces of the trench. Such processes are disclosed, for example, in Wolf, Volume 2, cited above.
In spite of its success, several limitations of LOCOS technology have driven the development of improved or alternative isolation structures. As further shown in FIG. 2, active area features 36, defined by the resulting FOX growth, often differ from the intended structure 38 because of nonideal effects present in conventional LOCOS processing. For example, light diffraction and interference around photolithographic mask edges during the patterning process typically produces, rounding at mask corners, an effect which is exacerbated in small features such as, found in DRAM active area arrays 30. Additionally, isolated, narrow photolithographic features such as shown here are often susceptible to lifting and nonconformities due to mask misalignment.
A major limitation in LOCOS isolation is that of oxide undergrowth or encroachment at the edge of the masking stack segment 32. A cross-section 2A--2A of the FOX structure after LOCOS isolation, shown in FIG. 2A, illustrates the deleterious effects of the encroachment, often referred to as a "bird's beak" 40 due to its sharp, tapering edge profile. This bird's beak 40 poses a serious limitation to device density, since that portion of the oxide adversely influences device performance while not significantly contributing to device isolation. Furthermore, as IC device density increases, the undesirable effects of bird's beak growth become particularly problematic for active area features in the sub half-micron regime. As shown in FIG. 2A, the bird's beak 40 of FOX regions 31 may extend beneath a substantial portion of mask regions 33 or 35 near the end or terminating portion of an active area. The bird's beak 40 becomes particularly severe at narrow, terminating features, often causing masking stack lifting and increasing stress-induced defects in the wafer. The bird's beak 40 also reduces the active area 36 on which devices can be fabricated directly in the bulk silicon 20, such that a large area of the chip is typically lost after field oxidation is complete.
Unfortunately, various techniques augmenting the basic LOCOS process are often accompanied by undesirable side effects or undue process complexity. For example, in DRAM fabrication technology, conventional LOCOS processes are often scaled for smaller device dimensions. This may be accomplished by increasing the thickness of the nitride 24 and reducing the thickness of the pad oxide 23 to reduce the FOX encroachment. However, this may increase stress in the nitride 24 as well as the underlying silicon 20, creating crystal defects which increase device junction leakage. On the other hand, if the nitride 24 thickness is not increased, stack lifting causes unpredictable changes in the shape of the active areas, particularly at the edges of the small features (i.e., active areas) typically found in DRAM applications.
In the continuing trend toward higher density and higher performance integrated circuits, effective field isolation on a sub-micron scale remains one of the most difficult challenges facing current process technology. While conventional LOCOS processes have sufficed in the past, there remains a critical need for improved field isolation.